[WIP] Update mlir-aie to latest nightly (1.4.2.dev12) and reduce IRON/mlir-aie duplication - #150
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[WIP] Update mlir-aie to latest nightly (1.4.2.dev12) and reduce IRON/mlir-aie duplication#150hunhoffe wants to merge 6 commits into
hunhoffe wants to merge 6 commits into
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v1.4.0 carries two breaking changes that the pinned v1.3.5.dev20 predates, so the version bump alone does not build. mlir-aie #3387 reworked the IRON Runtime into a callback body. Runtime() plus 'with rt.sequence(...)' is gone; the constructor now takes (seq_fn, fn_args), fill/drain moved onto the ObjectFifo handle, workers moved to Program(workers=), task_group()/finish_task_group() became TaskGroup()/tg.finish(), set_barrier() became barrier.set(), inline_ops() became a direct call, enable_trace() moved to Program and sync_parameters() to module scope. The per-transfer tile= argument is now bound on .prod()/.cons(), since placement is a property of the handle. mlir-aie #3364 unified aiecc's output selection under --get-<name>, removing --aie-generate-xclbin, --aie-generate-npu-insts and --no-compile-host. Asking only for the insts is what --no-compile used to mean, so that flag goes away rather than being renamed. Two spots needed more than a rename. gemm returns tensor access patterns that are recorded while the sequence body runs, and the body now runs at resolve_program() rather than at construction, so the program is resolved before the taps are read. mem_copy guarded rt.start on 'not bypass', which becomes a conditional workers= argument. Verified on Strix (npu2): the axpy suite passes 20/20 on device.
…0.2026081401 Builds on #145's v1.4.0 migration. Fixes further upstream breaking changes: - aiecc flipped its Peano/Chess default; --no-xchesscc/--no-xbridge no longer exist, so drop them (Peano is now the implicit default) - XRTTensor's residency tracking was reworked into a Storage/coherence-map model; XRTSubBuffer now shares its parent's _storage instead of bootstrapping incompatible state - drop --dynamic-objFifos everywhere it was passed (default upstream now) Also fixes iron/operators/__init__.py unconditionally importing the stream-dse-backed operator, which broke its documented self-skip behavior when onnx/stream-dse aren't installed. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware (some extensive failures under -n auto were pre-existing xdist build-directory races, confirmed passing when rerun serially). Co-Authored-By: Claude <noreply@anthropic.com>
mlir-aie's nightly (1.4.2.dev12) added a first-class subview() API backed by a shared storage/coherence map between a view and its parent. This directly supersedes XRTSubBuffer, which existed only because that capability didn't exist upstream (per its own TODO). Deleting it also fixes a real bug it had: XRTSubBuffer.to() always resynced the *entire* parent buffer, which could clobber a sibling sub-view whose fresh device data hadn't been read back yet. subview()'s shared coherence map tracks dirtiness per byte range instead, so each view's .to() only moves what it needs to. Converts all six call sites (iron/common/sequence.py, and four in llama_npu.py) from XRTSubBuffer(...)/XRTSubBuffer.from_parent(...) to parent.subview(offset_bytes, shape, dtype), then deletes the class. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware. llama_npu.py's call sites are syntax/import-checked only; no model weights available locally to run it end-to-end. Co-Authored-By: Claude <noreply@anthropic.com>
…_arch() get_kernel_dir() reimplemented the device-arch-to-kernel-dir-string mapping that mlir-aie's aie.utils.compile.utils.resolve_target_arch() now provides. Keep our own no-arg auto-detect default (resolve_target_arch(None) returns "aie2" unconditionally rather than checking the current device, which would silently regress every no-arg call site on NPU2 hardware), but delegate the actual device->arch-string logic once a concrete device is known. Verified: 2830/2830 operator tests pass on NPU2 hardware. Co-Authored-By: Claude <noreply@anthropic.com>
Contributor
CI Test Results0e9b53e (2026_08_14_17_42_59) IRON - CI SummarySmalliron/operators/axpy
iron/operators/dequant
iron/operators/elementwise_add
iron/operators/elementwise_mul
iron/operators/gelu
iron/operators/gemm
iron/operators/gemv
iron/operators/layer_norm
iron/operators/leaky_relu
iron/operators/mem_copy
iron/operators/relu
iron/operators/rms_norm
iron/operators/rope
iron/operators/sigmoid
iron/operators/silu
iron/operators/softmax
iron/operators/swiglu_decode
iron/operators/swiglu_prefill
iron/operators/tanh
iron/operators/transpose
Phoenix - SmallIRONTested on iron/operators/axpy
iron/operators/dequant
iron/operators/elementwise_add
iron/operators/elementwise_mul
iron/operators/gelu
iron/operators/gemm
iron/operators/gemv
iron/operators/layer_norm
iron/operators/leaky_relu
iron/operators/mem_copy
iron/operators/relu
iron/operators/rms_norm
iron/operators/rope
iron/operators/sigmoid
iron/operators/silu
iron/operators/softmax
iron/operators/swiglu_decode
iron/operators/swiglu_prefill
iron/operators/tanh
iron/operators/transpose
Trends: IRON Trendsiron/operators/axpytest_axpy[input_length_2048-num_aie_columns_1-tile_size_2048-scalar_factor_3.0]
test_axpy[input_length_2048-num_aie_columns_2-tile_size_1024-scalar_factor_3.0]
test_axpy[input_length_2048-num_aie_columns_4-tile_size_512-scalar_factor_3.0]
iron/operators/dequanttest_dequant[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-group_size_32]
test_dequant[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-group_size_32]
test_dequant[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-group_size_32]
test_dequant[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-group_size_32]
test_dequant[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-group_size_32]
test_dequant[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256-group_size_32]
iron/operators/elementwise_addtest_elementwise_add[input_length_2048-num_aie_columns_1-tile_size_2048]
test_elementwise_add[input_length_2048-num_aie_columns_2-tile_size_1024]
test_elementwise_add[input_length_2048-num_aie_columns_4-tile_size_512]
iron/operators/elementwise_multest_elementwise_mul[input_length_2048-num_aie_columns_1-tile_size_2048]
test_elementwise_mul[input_length_2048-num_aie_columns_2-tile_size_1024]
test_elementwise_mul[input_length_2048-num_aie_columns_4-tile_size_512]
iron/operators/gelutest_gelu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048]
test_gelu[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024]
test_gelu[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024]
test_gelu[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512]
test_gelu[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512]
test_gelu[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256]
iron/operators/gemmtest_gemm[M_192-K_384-N_64-num_aie_columns_4-b_col_maj_False-c_col_maj_False-m_48-k_96-n_16-trace_size_0-partition_N_1]
test_gemm[M_192-K_384-N_64-num_aie_columns_4-b_col_maj_True-c_col_maj_True-m_48-k_96-n_16-trace_size_0-partition_N_1]
test_gemm[M_2048-K_2048-N_2048-num_aie_columns_1-b_col_maj_False-c_col_maj_False-m_64-k_64-n_64-trace_size_0-partition_N_1]
test_gemm[M_2048-K_2048-N_2048-num_aie_columns_2-b_col_maj_True-c_col_maj_False-m_64-k_64-n_64-trace_size_0-partition_N_1]
test_gemm[M_384-K_1536-N_1792-num_aie_columns_4-b_col_maj_True-c_col_maj_False-m_32-k_48-n_64-trace_size_0-partition_N_1]
test_gemm[M_64-K_512-N_256-num_aie_columns_4-b_col_maj_True-c_col_maj_False-m_16-k_64-n_64-trace_size_0-partition_N_4]
iron/operators/gemvtest_gemv[M_128-K_128-num_aie_columns_1-tile_size_input_32-tile_size_output_128]
test_gemv[M_2048-K_8192-num_aie_columns_1-tile_size_input_1-tile_size_output_2048]
test_gemv[M_2048-K_8192-num_aie_columns_2-tile_size_input_1-tile_size_output_1024]
test_gemv[M_2048-K_8192-num_aie_columns_4-tile_size_input_1-tile_size_output_512]
test_gemv[M_8192-K_2048-num_aie_columns_1-tile_size_input_4-tile_size_output_1024]
test_gemv[M_8192-K_2048-num_aie_columns_2-tile_size_input_4-tile_size_output_1024]
test_gemv[M_8192-K_2048-num_aie_columns_4-tile_size_input_4-tile_size_output_1024]
test_gemv_batched[M_1024-K_1024-num_aie_columns_1-tile_size_input_1-tile_size_output_64-num_batches_2]
test_gemv_batched[M_1026-K_64-num_aie_columns_1-tile_size_input_1-tile_size_output_2-num_batches_2]
test_gemv_batched[M_256-K_128-num_aie_columns_1-tile_size_input_1-tile_size_output_256-num_batches_4]
test_gemv_batched[M_64-K_1536-num_aie_columns_1-tile_size_input_1-tile_size_output_64-num_batches_8]
test_gemv_gelu[M_128-K_128-num_aie_columns_1-tile_size_input_32-tile_size_output_128]No metrics available. test_gemv_gelu[M_2048-K_8192-num_aie_columns_1-tile_size_input_1-tile_size_output_2048]No metrics available. test_gemv_gelu[M_8192-K_2048-num_aie_columns_1-tile_size_input_4-tile_size_output_1024]No metrics available. iron/operators/layer_normtest_layer_norm[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048]
test_layer_norm[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024]
test_layer_norm[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024]
test_layer_norm[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512]
test_layer_norm[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512]
test_layer_norm[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256]
iron/operators/leaky_relutest_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-alpha_0.1]
test_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-alpha_0.25]
test_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256-alpha_0.01]
iron/operators/mem_copytest_mem_copy[input_length_2048-num_cores_1-num_channels_1-bypass_False-tile_size_2048]
test_mem_copy[input_length_2048-num_cores_2-num_channels_1-bypass_False-tile_size_1024]
test_mem_copy[input_length_2048-num_cores_2-num_channels_2-bypass_False-tile_size_1024]
test_mem_copy[input_length_2048-num_cores_4-num_channels_1-bypass_False-tile_size_512]
test_mem_copy[input_length_2048-num_cores_4-num_channels_2-bypass_False-tile_size_512]
test_mem_copy[input_length_2048-num_cores_8-num_channels_2-bypass_False-tile_size_256]
iron/operators/rms_normtest_rms_norm[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256-weighted_False]
iron/operators/ropetest_rope[rows_32-cols_512-angle_rows_32-aie_columns_1-method_type_0]
test_rope[rows_32-cols_512-angle_rows_32-aie_columns_2-method_type_0]
test_rope[rows_32-cols_512-angle_rows_32-aie_columns_4-method_type_0]
test_rope[rows_32-cols_512-angle_rows_8-aie_columns_1-method_type_0]
test_rope[rows_32-cols_512-angle_rows_8-aie_columns_2-method_type_0]
test_rope[rows_32-cols_512-angle_rows_8-aie_columns_4-method_type_0]
iron/operators/softmaxtest_softmax[input_length_32768-num_aie_columns_2-num_channels_2-tile_size_1024]
test_softmax[input_length_32768-num_aie_columns_2-num_channels_2-tile_size_2048]
test_softmax[input_length_32768-num_aie_columns_2-num_channels_2-tile_size_512]
iron/operators/swiglu_decodetest_swiglu_decode[embedding_dim_1024-hidden_dim_3584]
test_swiglu_decode[embedding_dim_2048-hidden_dim_2048]
iron/operators/swiglu_prefilltest_swiglu_prefill[seq_len_256-embedding_dim_2048-hidden_dim_2048-prio_accuracy_False]
iron/operators/transposetest_transpose[M_2048-N_64-aie_columns_1-channels_1-m_64-n_64-s_8-num_batches_1]
test_transpose[M_2048-N_64-aie_columns_1-channels_1-m_64-n_64-s_8-num_batches_2]
test_transpose[M_2048-N_64-aie_columns_1-channels_1-m_64-n_64-s_8]
test_transpose[M_2048-N_64-aie_columns_1-channels_2-m_64-n_64-s_8-num_batches_1]
test_transpose[M_2048-N_64-aie_columns_1-channels_2-m_64-n_64-s_8]
Phoenix - ExamplesIRONTested on Trends: IRON Trends |
Replaces the hand-built clang++/xchesscc invocation in KernelCompilationRule.compile() with aie.utils.compile.utils's compile_cxx_core_function(), wrapped in PythonCallbackCompilationCommand (which exists precisely for this: an arbitrary Python callable deferred into the same plan/execute contract as ShellCompilationCommand). This looked architecturally blocked at first (IRON's compile() methods return commands for a separate execute() step, while upstream's function runs synchronously), but IRON's execute() is already fully sequential in Python -- the only real parallelism is aiecc's own internal -j flag inside a single invocation, which is unaffected here since this rule only compiles individual kernel objects, not the aiecc/xclbin step. Nothing is lost by switching to a blocking call under a deferred wrapper. peano_dir/mlir_aie_dir were already always sourced from aie.utils.config.peano_install_dir()/root_path() (iron/common/context.py), the same config module the upstream function reads internally, so there's no override capability to lose. xchesscc_wrapper resolves via `shutil.which` upstream instead of an absolute path IRON constructed itself, but the wheel install puts it on PATH (ironenv/bin/xchesscc_wrapper), so this is a non-issue in the standard install. -Wno-missing-template-arg-list-after-template-kw is kept as an IRON-side extra flag (Peano-only, matching prior behavior) since it's specific to our kernel sources and upstream's default flag list doesn't include it. Symbol renaming/prefixing for operator fusion (_rename_symbols/ _prefix_symbols) stays IRON-side; upstream has no equivalent multi-symbol bulk-prefix operation. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware, including a from-scratch rebuild (rm -rf build/) to exercise every kernel compile through the new path. The use_chess=True path is unexercised by any test (also true before this change). Co-Authored-By: Claude <noreply@anthropic.com>
Replaces the hand-built aiecc invocation in AieccXclbinInstsCompilationRule and AieccFullElfCompilationRule with aie.utils.compile.utils's compile_mlir_module(), wrapped in PythonCallbackCompilationCommand (same pattern as the prior KernelCompilationRule change). Two real gaps had to be worked around, not just papered over: - compile_mlir_module() always names its own copy of the MLIR source "aie.mlir" inside a work_dir it controls, rather than accepting an existing file path. IRON's build previously kept every artifact's .mlir file (and aiecc's ".prj" companion) at a distinctive flat filename in one shared build/ directory. Introduced _aiecc_work_dir(), giving each MLIR source its own "<name>.mlir.d/" subdirectory, and updated the one place that depended on the old "<name>.mlir.prj" convention (OperatorSequence's params.txt lookup in sequence.py) to derive the new path the same way. - aiecc resolves an MLIR module's relative kernel-object references (e.g. link_with = "axpy.o") against that work_dir, not against the flat build_dir where KernelCompilationRule/ArchiveCompilationRule actually produced them. Added _link_build_outputs_into() to symlink the build directory's existing outputs into each artifact's work_dir before compiling, rather than reworking where kernel objects get built. Known, accepted regression: compile_mlir_module() resolves aiecc via aie.utils.compile.utils's own config.aiecc_path(), which does not honor the AIECC_PATH env var IRON previously supported for pointing a build at a locally-built aiecc without reinstalling the wheel. No test exercises this, but it's a real dev-workflow feature being dropped, not just an implementation detail. peano_dir/mlir_aie_dir/build_dir are no longer threaded into AieccCompilationRule's constructor (dead after this change), simplifying the context.py call sites accordingly. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware, from a clean build/ (rm -rf) to exercise every aiecc invocation through the new path, and again from a warm cache. Co-Authored-By: Claude <noreply@anthropic.com>
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mlir_aieto the latest nightly (1.4.2.dev12+ga5b4788, on top of Update mlir-aie to v1.4.0 and migrate the operator library to its APIs #145's v1.4.0 migration) andllvm-aieto22.0.0.2026081401(LLVM 21→22).--no-xchesscc/--no-xbridgeno longer exist), andXRTTensor's residency tracking was reworked into a shared storage/coherence-map model.--dynamic-objFifoseverywhere it was passed — it's the default upstream now.subview()API that fully supersedes our hand-rolledXRTSubBufferclass (it even resolves a FIXME we had:XRTSubBuffer.to()used to resync the entire parent buffer, clobbering sibling sub-views). Migrated all six call sites and deleted the class.get_kernel_dir()'s device→arch-string mapping now delegates to upstream'sresolve_target_arch()instead of reimplementing it.iron/operators/__init__.pyunconditionally imported the stream-dse-backed operator, which broke its documented self-skip behavior whenonnx/stream-dsearen't installed.PR Merge Checklist
develcommit and pointing todevel.